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• Javed Barkatullah
• Patents by Javed Barkatullah
• Clock Deskew
• Clock Inaccuracy
• Power Consumption Reduction
• Clock Dutycycle Correction

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Written by Javed Barkatullah

Category: About

1. Apparatus for power consumption reduction,  Patent Number: US 7562316
2. Frequency management apparatus, systems, and methods,  Patent Number: US 7282966
3. Clock modulation circuits with time averaging, Patent Number: US 20070238434
4. PLL with controlled VCO bias, Patent Number: US 20070046343
5. Method and apparatus for power consumption reduction, Patent Number: US 20060259890
6. Method for power consumption reduction, Patent Number: US 7096433
7. Frequency management apparatus, systems, and methods, Patent Number: US 20060066376
8. Adaptive body bias for clock skew compensation, Patent Number: US 7015741
9. Adaptive frequency clock generation system, Patent Number: US 20050218955
10. Method and apparatus for detecting on-die voltage variations, Patent Number: US 20050184764
11. Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise, Patent Number: US 6934872
12. Adaptive body bias for clock skew compensation, Patent Number: US 20050134361
13. Method and apparatus for power consumption reduction, Patent Number: US 20050102642
14. Digital clock skew detection and phase alignment, Patent Number: US 6622255
15. Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise, Patent Number: US 20030115493
16. Method and apparatus for synchronizing clock signals in a multiple die circuit including a stop clock feature, Patent Number: US 5706485
17. Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise, Patent Number: US 693487
18. Adaptive frequency clock signal, Patent Number: US 6922111
19. Clock signal generation and distribution via ring oscillators, Patent Number: US 6922112
20. Method and apparatus for detecting on-die voltage variations, Patent Number: US 6882238
21. Method and apparatus for correcting a clock duty cycle in a clock distribution network, Patent Number: US 6750689
22. Automated clock alignment for testing processors in a bypass mode, Patent Number: US 6704892
23. Generating a 2-phase clock using a non-50% divider circuit, Patent Number: US 6629255
24. Method and apparatus for generating 2/N mode bus clock signals, Patent Number: US 5821784
25. Core clock correction in a 2/N mode clocking scheme, Patent Number: US 5834956
26. Method and apparatus for generating 2/N mode bus clock signals, Patent Number:  US 6104219
27. Method and apparatus for clock skew compensation, Patent Number: US 6192092
28. Core clock correction in a 2/N mode clocking scheme, Patent Number: US 6208180
29. Core clock correction in a 2/n mode clocking scheme, Patent Number: US 6268749
30. Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit, Patent Number: US 6611920

• Javed Barkatullah
• Barkatech
• Consulting

Details

Written by Javed Barkatullah

Category: About

Barkatech Consulting, LLC is a member of EE Consult Oregon, which is the Oregon chapter of the Alliance of IEEE Consultants' Networks (AICN), a nationwide organization of electrical and electronic consultants.

Dr. Javed Barkatullah is the Principal / Founder of Barkatech Consulting, LLC. He is a silicon design industry veteran with over 23 years of diverse research, design and management experience. Dr. Barkatullah is currently engaged as a consultant to Everspin Technologies, Inc. for the design and implementation of a new MRAM (Magnetic Random Access Memory) chip using spin-torque technology. His last project involved the research, design and implementation of high performance, power efficient custom ASICs and system for Bitcoin mining application for Cointerra, Inc. of Austin TX. Previously, he had worked on developing 2D to 3D conversion algorithms, software and hardware.

Dr. Barkatullah was a co-founder and CEO of a mobile social network marketing company, Gobenow, Inc. He designed and developed the business model, technology and apps for the mobile marketing platform. Previously, Dr. Barkatullah has served as Principal Engineer/Manager at Nvidia Corporation, member Technical Staff at Stexar Corporation, and Senior Principal Engineer at Intel Corporation. He is a visionary technologist, experienced business leader with strong interdisciplinary skills and expertise. He has expertise in research, design, implementation and verification of high performance circuits and in the management of technology projects. He has played leadership role in advanced microprocessors, video processors and graphics processors design projects.He received the Intel Achievement Award in 1996 for outstanding contributions to low power processor design.

Dr. Barkatullah received his Masters and PhD degrees in Electrical & Computer Engineering from University of Iowa, and an MBA degree from Willamette University. He also has a Certificate in Sustainable Enterprise from Willamette University. Dr. Barkatullah has over thirty patents in the field of high-speed circuit designs and has many technical publications in the IEEE journals. He has served as an associate editor of IEEE Journal of Solid State Electronics from June 2004 to October 2005.

List of US & International Patents By Dr. Javed Barkatullah

List of Publications by Dr. Javed Barkatullah