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      List of US & International Patents By Dr. Javed Barkatullah

      Written by Javed Barkatullah

       

      1. Apparatus for power consumption reduction,  Patent Number: US 7562316
      2. Frequency management apparatus, systems, and methods,  Patent Number: US 7282966
      3. Clock modulation circuits with time averaging, Patent Number: US 20070238434
      4. PLL with controlled VCO bias, Patent Number: US 20070046343
      5. Method and apparatus for power consumption reduction, Patent Number: US 20060259890
      6. Method for power consumption reduction, Patent Number: US 7096433
      7. Frequency management apparatus, systems, and methods, Patent Number: US 20060066376
      8. Adaptive body bias for clock skew compensation, Patent Number: US 7015741
      9. Adaptive frequency clock generation system, Patent Number: US 20050218955
      10. Method and apparatus for detecting on-die voltage variations, Patent Number: US 20050184764
      11. Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise, Patent Number: US 6934872
      12. Adaptive body bias for clock skew compensation, Patent Number: US 20050134361
      13. Method and apparatus for power consumption reduction, Patent Number: US 20050102642
      14. Digital clock skew detection and phase alignment, Patent Number: US 6622255
      15. Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise, Patent Number: US 20030115493
      16. Method and apparatus for synchronizing clock signals in a multiple die circuit including a stop clock feature, Patent Number: US 5706485
      17. Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise, Patent Number: US 693487
      18. Adaptive frequency clock signal, Patent Number: US 6922111
      19. Clock signal generation and distribution via ring oscillators, Patent Number: US 6922112
      20. Method and apparatus for detecting on-die voltage variations, Patent Number: US 6882238
      21. Method and apparatus for correcting a clock duty cycle in a clock distribution network, Patent Number: US 6750689
      22. Automated clock alignment for testing processors in a bypass mode, Patent Number: US 6704892
      23. Generating a 2-phase clock using a non-50% divider circuit, Patent Number: US 6629255
      24. Method and apparatus for generating 2/N mode bus clock signals, Patent Number: US 5821784
      25. Core clock correction in a 2/N mode clocking scheme, Patent Number: US 5834956
      26. Method and apparatus for generating 2/N mode bus clock signals, Patent Number:  US 6104219
      27. Method and apparatus for clock skew compensation, Patent Number: US 6192092
      28. Core clock correction in a 2/N mode clocking scheme, Patent Number: US 6208180
      29. Core clock correction in a 2/n mode clocking scheme, Patent Number: US 6268749
      30. Clock distribution system for selectively enabling clock signals to portions of a pipelined circuit, Patent Number: US 6611920
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