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  1. Goldstrike 1(TM): Cointerra’s First Generation Crypto-currency Mining Processor for Bitcoin: Javed Barkatullah, Timo Hanke, IEEE Micro, Issue 99, pp .
  2. Goldstrike 1(TM): Cointerra’s First Generation Crypto-currency Processor for Bitcoin Mining Machines : Javed Barkatullah, Timo Hanke, Ravi Iyengar, Ricky Lewelling, Jim O’Connor, Hot Chips Symposium HC26, Aug. 10-12,  2014.
  3. Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses: Maged Ghoneima, Muhammad Khellah, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Yehea Ismail, Vivek De ; IEEE Transactions on Circuits & Systems, 2008, vol. 55, issue 7, pp 1904-1910.
  4. A Skewed Repeater Bus Architecture Technique for On Chip Energy Reduction in Microprocessors: Muhammad Khellah,  Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Yehea Ismail, Vivek De ; ICCD 2005, pp 253-257.
  5. Reducing the Impact of Power Supply Noise on Microprocessor Performance: Tawfik Rahal-Arabi, Keng L. Wong, Javed Barkatullah, Matthew Ma, Greg Taylor, IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging 2005, pp 307-310.
  6. Enhancing microprocessor immunity to power supply noise with clock/data compensation: Tawfik Rahal-Arabi, Greg Taylor, Javed Barkatullah, Keng L. Wong, Matthew Ma,  IEEE Symposium on VLSI Circuits, June 16-18 2005, pages 16-19.
  7. A Design for Digital, Dynamic Clock Deskew: Charles E. Dike, Nasser A. Kurd, Priyadarsan Patra, Javed Barkatullah, ; 2003 Symposium on VLSI Circuits, Digest of Technical Papers, pp 21-24.
  8. A Replica-biased 50% Duty Cycle PLL Architecture with 1x VCO: Nasser Kurd, Jed Griffin, Javed. Barkatullah, Ian Young; IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers, 9-13 Feb. 2003, Pages:426 - 504 vol.1
  9. NWD 1XVCO Replica-Biased PLL: Nasser A. Kurd, Jed Griffin, Javed Barkatullah, Ian Young; DTTC 2003.
  10. A Digital Dynamic Mesh Deskew and Its Stability Criteria: Charles E. Dike, Nasser A. Kurd, Priyadarsan Patra, Javed Barkatullah, DTTC 2002
  11. Multi-GHz Clocking Scheme for Intel(R) Pentium(R) 4 microprocessor: Nasser Kurd, Javed Barkatullah, Rommel Dizon, Tom Fletcher, Paul Madland; IEEE International Solid-State Circuits Conference, 2001. Digest of Technical Papers, 5-7 Feb. 2001; Pages:404 – 405.
  12. Estimation of Clock Inaccuracy for High Speed Chip Design: Javed Barkatullah, Paul Madland;  Proceedings Intel Design,Test & Technology Conference, pp. 285-289, July 1997.
  13. High-speed Digital Circuit Timing Race Modeling: Sammie Samaan, Milo Sprague, Javed Barkatullah; Proceedings Intel Design,Test & Technology Conference, pp. 291-296, July 1997.
  14. Management of Power Supply Noise Using Die, Package and Board Level Solutions: Tom Mozden, Javed Barkatullah, S. Rajgopal, D. Weiss; Intel Technology Journal, pp 49-61, Fall 1995.
  15. Domino Logic Design Using Cells: Tom Fletcher, Javed. Barkatullah, A. Dedhia; Proceedings Intel Design, Test and Technology Conference,  pp 91-94, June 1993.
  16. A Transmission Line Simulator for High-speed Interconnects: Salim Chowdhury, Javed Barkatullah, D. Zhou, E. W. Bai, K. E. Lonngren;  IEEE Transactions on Analog and Digital Signal Processing,  Volume: 39 , Issue: 4 , April 1992; Pages:201 – 211
  17. Transient Analysis of Lossy Transmission Lines in Integrated Circuits: Javed Barkatullah, Salim Chowdhury; IEEE International Symposium on Circuits and Systems, 1992. Proceedings Volume: 5, 3-6 May 1992; Pages:2352 - 2355 vol.5.
  18. An Efficient Method for Computing Transient response of Integrated Circuits with Lossy Transmission Lines:  Salim Chowdhury, Javed Barkatullah, ; Proceedings [3rd] European Conference on Design Automation, 1992, 16-19 March 199 ; Pages:219 – 223.
  19. A Transmission Line Simulator for GaAs Integrated Circuits: Javed Barkatullah, Salim Chowdhury; 28th ACM/IEEE Design Automation Conference, June 17-21, 1991; Pages:746 – 751
  20. Estimation of Maximum Currents in MOS IC Logic Circuits: Salim Chowdhury, Javed Barkatullah, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume: 9 , Issue: 6, June 1990; Pages:642 – 654.
  21. Current Estimation in MOS IC Logic Circuits: Salim Chowdhury, Javed Barkatullah.; IEEE International Conference on Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers, 7-10 Nov. 1988; Pages:212 - 215

 

 

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